AT89S4D12-12JC View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT89S4D12-12JC

8-Bit Microcontroller with 132K Bytes Flash Data Memory

Atmel Corporation 

AT89S4D12

Serial Peripheral Interface

The serial peripheral interface (SPI) allows high-speed syn-

chronous data transfer between the AT89S4D12 and an

SPI master. The AT89S4D12 SPI features include the fol-

lowing:

• Full-Duplex, 3-Wire Synchronous Data Transfer

• 2 MHz Bit Frequency (max.)

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

The interconnection between master and slave CPU with

SPI is shown in the following figure. The SCK pin is the

clock input. Writing to the SPI data register of the master

CPU starts the SPI clock generator, and the data written

shifts out of the MOSI pin and into the SDI pin of the slave

CPU. After shifting one byte, the SPI clock generator stops,

setting the end of transmission flag (SPIF). If the SPI inter-

rupt enable bit (SPIE) is set, an interrupt is requested.

There are four combinations of SCK phase and polarity

with respect to serial data, which are determined by control

bits CPHA and CPOL. The SPI data transfer formats are

shown in Figure 3 and Figure 4.

Figure 1. SPI Block Diagram

SDO

P1.0

OSCILLATOR

SDI

MSB

LSB

P1.1

8/16-BIT SHIFT REGISTER

DIVIDER

÷4÷16÷64÷128

READ DATA BUFFER

CLOCK

SELECT

SPI CLOCK (MASTER)

CLOCK

SCK

P1.3

LOGIC

SPI CONTROL

SPI STATUS REGISTER

SPE

8

SPI CONTROL REGISTER

8

8

SPI INTERRUPT INTERNAL

REQUEST DATA BUS

4-287

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