SAF-C167CR-16RM View Datasheet(PDF) - Siemens AG
Part Name
Description
Manufacturer
SAF-C167CR-16RM Datasheet PDF : 67 Pages
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20Dec96@09:25h Intermediate Version
C167CR-16RM
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CR-16RM’s instructions can be executed in
just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
13
Semiconductor Group
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