DSP56001 Electrical Characteristics
AC Electrical Characteristics - SSI Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see SSI Figures 1 and 2)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tSSICC = SSI clock cycle time
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) = Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
g ck = Gated Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and
RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and
RXC are the same clock)
bl = bit length
wl = word length
Num
Characteristics
20.5 MHz
Min
Max
80 Clock Cycle (see Note 1)
4 cyc
—
*
81 Clock High Period
2 cyc-20
—
*
82 Clock High Period
2 cyc-20
—
*
84 RXC Rising Edge to FSR Out (bl) High
x ck
—
80
i ck a
—
50
85 RXC Rising Edge to FSR Out (bl) Low
x ck
—
70
i ck a
—
40
86 RXC Rising Edge to FSR Out (wl) High
x ck
—
70
i ck a
—
40
87 RXC Rising Edge to FSR Out (wl) Low
x ck
—
70
i ck a
—
40
88 Data In Setup Time Before RXC (SCK
in Synchronous Mode) Falling Edge
x ck
15
—
i ck a
35
—
i ck s
25
—
89 Data In Hold Time After RXC Falling
Edge
x ck
35
—
i ck a
5
—
90 FSR Input (bl) High Before RXC Falling
Edge
x ck
15
—
i ck a
35
—
91 FSR Input (wl) High Before RXC
Falling Edge
x ck 20
—
i ck a
55
—
92 FSR Input Hold Time After RXC Falling
Edge
x ck
35
—
i ck a
5
—
27 MHz
Min
Max
4 cyc
—
*
2 cyc-15
—
*
2 cyc-15
—
*
—
61
—
38
—
54
—
31
—
54
—
31
—
54
—
31
12
—
27
—
19
—
27
—
4
—
12
—
27
—
15
—
42
—
27
—
4
—
33 MHz
Min
Max
4 cyc
—
*
2 cyc-13
—
*
2 cyc-13
—
*
—
48
—
31
Unit
ns
ns
ns
ns
ns
—
43
ns
—
25
ns
—
43
ns
—
25
ns
—
43
ns
—
25
ns
10
—
ns
22
—
ns
16
—
ns
22
—
ns
4
—
ns
10
—
ns
23
—
ns
13
—
ns
34
—
ns
22
—
ns
4
—
ns
MOTOROLA
28
DSP56001