DSP56001 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56001

24-Bit General Purpose Digital Signal Processor

Motorola => Freescale 

DSP56001 Electrical Characteristics

AC Electrical Characteristics - SSI Timing (Continued)

Note:

1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.

Num

Characteristics

20.5 MHz

27 MHz

33 MHz

Min

Max

Min

Max

Min

Max

93 Flags Input Setup Before RXC Falling

Edge

x ck 30

—

23

—

19

—

i ck a 50

—

39

—

31

—

94 Flags Input Hold Time After RXC

Falling Edge

x ck

35

—

27

—

22

—

i ck a

5

—

4

—

4

—

95 TXC Rising Edge to FST Out (bl) High

x ck

—

70

—

54

—

43

i ck a —

30

—

23

—

19

96 TXC Rising Edge to FST Out (bl) Low

x ck

—

65

—

50

—

40

i ck a —

35

—

27

—

22

97 TXC Rising Edge to FST Out (wl) High

x ck

—

65

—

50

—

40

i ck a —

35

—

27

—

22

98 TXC Rising Edge to FST Out (wl) Low

x ck

—

65

—

50

—

40

i ck a —

35

—

27

—

22

99 TXC Rising Edge to Data Out Enable

from High Impedance

x ck

—

65

—

50

—

40

i ck a —

40

—

31

—

25

100 TXC Rising Edge to Data Out Valid

x ck

—

65

—

50

—

40

i ck a —

40

—

31

—

25

101 TXC Rising Edge to Data Out High

Impedance (periodically sampled, and

not 100% tested)

x ck

—

70

—

54

—

43

i ck a —

40

—

31

—

25

101a TXC Falling Edge to Data Out High

Impedance for Gated Clock Mode Only

g ck cyc+tch

—

cyc+tch

—

cyc+tch

—

102 FST Input (bl) Setup Time Before TXC

Falling Edge

x ck

15

—

12

—

10

—

i ck a

35

—

27

—

23

—

103 FST Input (wl) to Data Out Enable from

—

60

—

46

—

37

High Impedance

104 FST Input (wl) Setup Time Before TXC

Falling Edge

x ck

20

—

15

—

13

—

i ck a 55

—

42

—

34

—

105 FST Input Hold Time After TXC Falling

Edge

x ck 35

—

27

—

22

—

i ck a

5

—

4

—

4

—

106 Flag Output Valid After TXC Rising

Edge

x ck

—

70

—

54

—

43

i ck a —

40

—

31

—

25

Unit

ns

nss

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note:

1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.

DSP56001

MOTOROLA

29

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