IS42LS16800A View Datasheet(PDF) - Integrated Circuit Solution Inc

Part Name

Description

Manufacturer

IS42LS16800A

16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

Integrated Circuit Solution Inc 

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI ®

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min. Max. Unit

IIL

Input Leakage Current

0V ≤ VIN ≤ VDD, with pins other than

the tested pin at 0V

–5

5

µA

IOL

Output Leakage Current

Output is disabled, 0V ≤ VOUT ≤ VDD

–5

5

µA

VOH

Output High Voltage Level

IOUT = –2 mA

2.4

—

V

VOL

Output Low Voltage Level

IOUT = +2 mA

— 0.4

V

IDD1

Operating Current(1,2)

One Bank Operation,

Burst Length=1

tRC ≥ tRC (min.)

IOUT = 0mA

CAS latency = 3

Com. -7

— 120 mA

Ind. -7

— 140 mA

Com. -10 — 110 mA

Ind. -10 — 120 mA

IDD2P

IDD2PS

Precharge Standby Current

(In Power-Down Mode)

CKE ≤ VIL (MAX)

tCK = tCK(MIN) Com. —

—

1

mA

Ind. —

—

1

mA

tCK = ∞

Com. —

—

.6

mA

Ind. —

—

.6

mA

IDD2N

IDD2NS

Precharge Standby Current

(In Non Power-Down Mode)

CKE ≥ VIH (MIN)

tCK = tCK (MIN)

—

—

11

mA

tCK = ∞

Com. —

—

5

mA

Ind. —

—

7

mA

IDD3P

IDD3PS

Active Standby Current

(In Power-Down Mode)

CKE ≤ VIL (MAX)

tCK = tCK(MIN) Com. —

—

4

mA

Ind.

Ind. —

—

6

mA

tCK = ∞

Com. —

—

3

mA

Ind. —

—

5

mA

IDD3N

IDD3NS

Active Standby Current

(In Non Power-Down Mode)

CKE ≥ VIH (MIN)

tCK = tCK (MIN)

—

—

28

mA

tCK = ∞

Com. —

—

17

mA

Ind. —

—

20

mA

IDD4

Operating Current

(In Burst Mode)(1)

tCK = tCK (MIN)

IOUT = 0mA

CAS latency = 3

Com. -7

— 120 mA

Ind. -7

— 140 mA

Com. -10 — 110 mA

Ind. -10 — 120 mA

CAS latency = 2

Com. -7

—

90

mA

Ind. -7

— 110 mA

Com. -10

—

80

mA

Ind. -10 — 100 mA

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time

increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and Vss for each memory

chip to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Idd1 and Idd4 depend on the output load. The maximum values for Idd1 and Idd4 are obtained with the output open state.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

19

ADVANCEDINFORMATION Rev. 00A

06/01/02

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