MAX1211(2003) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX1211 Datasheet PDF : 29 Pages
| |||
65Msps, 12-Bit, IF Sampling ADC
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 8pF at digital outputs, differential
input at -0.2dBFS, CLKTYP = high, PD = low, G/T = low, fCLK = 65.005678MHz (50% duty cycle), CREFP = CREFN = 0.1µF in parallel
with 10µF to GND, 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.)
OFFSET ERROR
vs. TEMPERATURE
0.080
VREFIN = 2.048V
0.075
0.070
0.065
0.060
-40 -15
10
35
60
85
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
2.0
VREFIN = 2.048V
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-40 -15
10
35
60
85
TEMPERATURE (°C)
Pin Description
PIN
1
2
3
4, 7, 16, 35
5
6
8, 12–15,
36
9
10
NAME
REFP
REFN
COM
GND
INP
INN
VDD
CLKN
CLKP
FUNCTION
Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a ≥2.2µF
capacitor in parallel with a 0.1µF capacitor. Connect a 10µF bypass capacitor between REFP and REFN.
Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a ≥2.2µF
capacitor in parallel with a 0.1µF capacitor. Connect a 10µF bypass capacitor between REFP and REFN.
Common-Mode Voltage I/O. Bypass COM to GND with a ≥2.2µF capacitor in parallel with a 0.1µF
capacitor.
Ground. Connect all ground pins and the EP together.
Positive Analog Input. For single-ended input operation, connect signal source to INP and connect INN
to COM. For differential operation, connect the input signal between INP and INN.
Negative Analog Input. For single-ended input operation, connect INN to COM. For differential operation,
connect the input signal between INP and INN.
Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the clock
signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the clock signal
to CLKP and tie CLKN to GND.
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
______________________________________________________________________________________ 15
Share Link: 