MAX3991UTG View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3991UTG

10Gbps Clock and Data Recovery with Limiting Amplifier

Maxim Integrated 

10Gbps Clock and Data Recovery

with Limiting Amplifier

50Ω

REFERENCE

CLOCK

50Ω

MAX3991

200Ω

REFERENCE

CLOCK

MAX3992

200Ω

MAX3991

50Ω

200Ω

200Ω

50Ω

RECEIVER-ONLY TERMINATION

TRANSCEIVER TERMINATION

Figure 5. Reference Clock Termination

Table 3. Functional Control

FCTL1

0

1

0

1

FCTL2

0

0

1

1

DESCRIPTION

Normal operation, serial clock output

disabled.

Standby power-down mode.

Serial data output disabled.

Serial clock output enabled for jitter

testing.

VCC

50Ω

50Ω

SDI+

SDI-

Applications Information

Exposed Pad (EP) Package

The exposed pad, 24-pin QFN incorporates features

that provide a very low thermal-resistance path for heat

removal from the IC. The pad is electrical ground on the

MAX3991 and must be soldered to the circuit board for

proper thermal and electrical performance.

Layout Considerations

For best performance, use good high-frequency layout

techniques. Filter voltage supplies, keep ground con-

nections short, and use multiple vias where possible.

Use controlled-impedance transmission lines to inter-

face with the MAX3991 high-speed inputs and outputs.

Power-supply decoupling should be placed as close to

VCC as possible. To reduce feedthrough, take care to

isolate the input signals from the output signals.

Figure 6. CML Input Model

10 ______________________________________________________________________________________

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