MT46V128M4TG-8 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT46V128M4TG-8

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the DDR SDRAM, a row in that

bank must be “opened.” This is accomplished via the

ACTIVE command, which selects both the bank and

the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) should

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock edge

after the ACTIVE command on which a READ or WRITE

command can be entered. For example, a tRCD specifi-

cation of 20ns with a 133 MHz clock (7.5ns period) re-

sults in 2.7 clocks rounded to 3. This is reflected in

Figure 5, which covers any case where 2 < tRCD (MIN)/

tCK ≤ 3. (Figure 5 also shows the same case for tRCD; the

same procedure is used to convert other specification

limits from time units to clock cycles).

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous

active row has been “closed” (precharged). The mini-

mum time interval between successive ACTIVE com-

mands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row-access over-

head. The minimum time interval between successive

ACTIVE commands to different banks is defined by

tRRD.

ADVANCE

512Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0-A12

RA

BA0,1

BA

RA = Row Address

BA = Bank Address

Figure 4

Activating a Specific Row in

a Specific Bank

T0

CK#

CK

COMMAND

ACT

T1

T2

T3

T4

NOP

NOP

ACT

NOP

T5

T6

T7

NOP

RD/WR

NOP

A0-A12

Row

Row

Col

BA0, BA1

Bank x

Bank y

Bank y

tRRD

tRCD

DON’T CARE

Figure 5

Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3

512Mb: x4, x8, x16 DDR SDRAM

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

16

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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