R8A77301 View Datasheet(PDF) - Renesas Electronics
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R8A77301 Datasheet PDF : 1188 Pages
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10.5.3 Interrupt Masking by MAI Bit ............................................................................... 272
10.5.4 Interrupt Disabling Function in User Mode ........................................................... 273
10.6 Interrupt Response Time................................................................................................... 274
10.7 Usage Notes ...................................................................................................................... 275
10.7.1 Notes on Level Sensing Interrupt........................................................................... 275
Section 11 Bus State Controller (BSC) ............................................................. 277
11.1 Features............................................................................................................................. 277
11.2 Input/Output Pins.............................................................................................................. 280
11.3 Area Overview.................................................................................................................. 282
11.3.1 Area Division ......................................................................................................... 282
11.3.2 Shadow Area .......................................................................................................... 282
11.3.3 Address Map .......................................................................................................... 284
11.3.4 Area 0 Memory Type and Memory Bus Width ..................................................... 287
11.3.5 Data Alignment ...................................................................................................... 287
11.4 Register Descriptions........................................................................................................ 288
11.4.1 Common Control Register (CMNCR) ................................................................... 290
11.4.2 CSn Space Bus Control Register (CSnBCR) ......................................................... 294
11.4.3 CSn Space Wait Control Register (CSnWCR)....................................................... 299
11.4.4 SDRAM Control Register (SDCR) ........................................................................ 323
11.4.5 Refresh Timer Control/Status Register (RTCSR) .................................................. 326
11.4.6 Refresh Timer Counter (RTCNT) .......................................................................... 328
11.4.7 Refresh Time Constant Register (RTCOR)............................................................ 329
11.4.8 SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3)........................................... 329
11.5 Operation .......................................................................................................................... 330
11.5.1 Endian/Access Size and Data Alignment............................................................... 330
11.5.2 Normal Space Interface.......................................................................................... 336
11.5.3 Access Wait Control .............................................................................................. 342
11.5.4 CSn Assert Period Expansion ................................................................................ 344
11.5.5 SDRAM Interface .................................................................................................. 345
11.5.6 Burst ROM (Clock Asynchronous) Interface......................................................... 383
11.5.7 Byte-Selection SRAM Interface ............................................................................ 385
11.5.8 PCMCIA Interface ................................................................................................. 390
11.5.9 Wait between Access Cycles ................................................................................. 398
11.5.10 Bus Arbitration....................................................................................................... 399
11.6 Usage Notes ...................................................................................................................... 401
Section 12 Direct Memory Access Controller (DMAC)................................... 403
12.1 Features............................................................................................................................. 403
12.2 Input/Output Pins.............................................................................................................. 405
Rev. 1.00 Sep. 19, 2007 Page xiv of xlviii
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