SST25VF080B View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST25VF080B

8 Mbit SPI Serial Flash

Silicon Storage Technology 

A Microchip Technology Company

8 Mbit SPI Serial Flash

SST25VF080B

Data Sheet

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP

(software data protection) command structure which prevents any accidental alteration of the status

register values. CE# must be driven low before the EWSR instruction is entered and must be driven

high before the EWSR instruction is executed.

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of

the status register. CE# must be driven low before the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN

and WRSR instruction sequences.

Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to

“1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock-down the status register,

but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled

and the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit

is set to 0 or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of

the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this

case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as

altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP#

and BPL functions.

CE#

MODE 3

SCK MODE 0

0 1 2345 6 7

SI

50 or 06

MSB

SO

MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MODE 0

01

MSB

HIGH IMPEDANCE

STATUS

REGISTER IN

76543210

MSB

1296 EWSR.0

Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and

Write-Status-Register (WRSR) Sequence

©2011 Silicon Storage Technology, Inc.

20

S71296-05-000

02/11

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