ST16C1450(2005) View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

ST16C1450
(Rev.:2005)

2.97V TO 5.5V UART

Exar Corporation 

ST16C1450

2.97V TO 5.5V UART

FIGURE 5. RECEIVER OPERATION IN NON-FIFO MODE

16X Clock

Receive Data Shift Data Bit

Register (RSR)

Validation

xr

REV. 4.2.1

Receive Data Characters

Receive

Data Byte

and Errors

Error

Tags in

LSR bits

4:2

Receive Data

Holding Register

(RHR)

RHR Interrupt (ISR bit-2)

RXFIFO1

2.6 Special (Enhanced Feature) Mode

The 1450 supports the standard features of the ST16C450. In addition, the 1450 supports some enhanced

features not available for the ST16C450. These features are enabled by IER bit-5 and include a software

controllable (SOFT) reset, power down feature and FIFO monitoring bits.

2.6.1 Soft Reset

Soft resets are useful when the user desires the capability of resetting an externally connected device only.

MCR bit-2 can be used to initiate a SOFT reset at the RST output pin. This does not reset the 1450 (only the

RESET input pin can reset the 1450). Soft resets from MCR bit-2 are “ORed” with the RESET input pin.

Therefore both reset types will be seen at the RST output pin.

2.6.2 Power Down Mode

The power down feature (controlled by MCR bit-7) provides the user with the capability to conserve power

when the package is not in actual use without destroying internal register configuration data. This allows quick

turnarounds from power down to normal operation. For complete details, see the MCR bit-7 description on

page 16.

2.7 Internal Loopback

The 1450 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 6 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and

CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback

test else upon exiting the loopback test the UART may detect and report a false “break” signal.

8

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