UPD754304GS-XXX-T2 View Datasheet(PDF) - NEC => Renesas Technology
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UPD754304GS-XXX-T2 Datasheet PDF : 335 Pages
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LIST OF FIGURES (1/3)
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Title
Page
Pin I/O Circuits ..................................................................................................................... 17
Selecting MBE = 0 Mode and MBE = 1 Mode ................................................................... 22
Data Memory Configuration and Addressing Range for Each Addressing Mode ............ 24
Static RAM Address Update Method .................................................................................. 30
Example of Using Register Banks ....................................................................................... 37
General-Purpose Register Configuration (for 4-bit operation) ........................................... 39
General-Purpose Register Configuration (for 8-bit operation) ........................................... 40
µPD754304 I/O Map ............................................................................................................ 43
Stack Bank Select Register Format .................................................................................... 50
Program Counter Structure .................................................................................................. 51
Program Memory Map ......................................................................................................... 54
Data Memory Map ................................................................................................................ 59
General-Purpose Register Configuration
Register Pair Configuration .................................................................................................. 62
Accumulators ........................................................................................................................ 63
Stack Pointer and Stack Bank Selection Register Configuration ...................................... 64
Data Saved in Stack Memory (Mk I mode) ......................................................................... 65
Data Restored from Stack Memory (Mk I mode) ................................................................ 65
Data Saved in Stack Memory (Mk II mode) ........................................................................ 66
Data Restored from Stack Memory (MkII mode) ................................................................ 66
Program Status Word Format .............................................................................................. 67
Bank Selection Register Format .......................................................................................... 71
Digital Ports Data Memory Addresses ................................................................................ 73
Port 0, 1 Configuration ......................................................................................................... 75
Port 2, 7 Configuration ......................................................................................................... 76
Port 3, Port 6 Configuration ................................................................................................. 77
Port 5 Configuration ............................................................................................................. 78
Port 8 Configuration ............................................................................................................. 79
Port Mode Register Formats ............................................................................................... 81
Pull-Up Resistor Specify Register Format .......................................................................... 88
I/O Timing of Digital I/O Port ............................................................................................... 89
ON Timing of On-Chip Pull-up Resistor Connected via Software ..................................... 90
Clock Generator Block Diagram .......................................................................................... 91
Processor Clock Control Register Format .......................................................................... 94
Main System Clock Oscillator External Circuit ................................................................... 95
Example of Connecting Resonator Incorrectly ................................................................... 96
Switching CPU Clock ........................................................................................................... 99
Clock Output Circuit Block Diagram .................................................................................... 100
Clock Output Mode Register Format ................................................................................... 101
Application Example of Remote Control Output ................................................................. 102
Basic Interval Timer/Watchdog Timer Block Diagram ........................................................ 103
Basic Interval Timer Mode Register Format ....................................................................... 105
User’s Manual U10123EJ2V1UM00
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