UPD754304GS-XXX-T2 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD754304GS-XXX-T2

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

LIST OF FIGURES (2/3)

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Watchdog Timer Enable Flag (WDTM) Format .................................................................. 106

Timer/Event Counter Block Diagram (channel 0) ............................................................... 114

Timer/Event Counter Block Diagram (channel 1) ............................................................... 115

Timer/Event Counter Mode Register (channel 0) Format .................................................. 117

Timer/Event Counter Mode Register (Channel 1) Format ................................................. 118

Timer/Event Counter Output Enable Flag Format .............................................................. 119

Timer/Event Counter Mode Register Setup (8-bit) ............................................................. 121

Format of the Timer/Event Counter Output Enable Flag ................................................... 123

Configuration of Timer/Event Counter ................................................................................. 125

Count Operation Timing ....................................................................................................... 126

Timer/Event Counter Mode Register Setup ........................................................................ 129

Format of the Timer/Event Counter Output Enable Flag ................................................... 130

16-bit Timer/Event Counter Operation Configuration ......................................................... 133

Count Operation Timing ....................................................................................................... 133

Serial Interface Block Diagram ............................................................................................ 141

Serial Operation Mode Register (CSIM) Format ................................................................ 144

Serial Bus Interface Control Register (SBIC) Format ........................................................ 147

System Comprising Shift Register and Peripheral Devices Configuration ...................... 148

Example of System Configuration in 3-Wire Serial I/O Mode............................................ 152

3-wire Serial I/O Mode Timing ............................................................................................. 155

Operation of RELT and CMDT ............................................................................................ 156

Transfer Bit Change Circuit ................................................................................................. 157

Example of System Configuration in 2-Wire Serial I/O Mode............................................ 162

2-wire Serial I/O Mode Timing ............................................................................................. 165

Operation of RELT and CMDT ............................................................................................ 166

SCK/P01 Pin Configuration ................................................................................................. 169

Bit Sequential Buffer Format ............................................................................................... 171

Interrupt Control Circuit Block Diagram .............................................................................. 174

Interrupt Vector Table .......................................................................................................... 175

Interrupt Priority Selection Register .................................................................................... 179

Configurations of INT0, INT1, and INT4 ............................................................................. 181

Noise Detection Circuit Input/Output Timing ...................................................................... 182

Edge Detection Mode Register Format ............................................................................... 183

Interrupt Processing Sequence ........................................................................................... 185

Multiple Interrupts by Higher-Order Priority Interrupts ....................................................... 186

Multiple Interrupts by Changing the Interrupt Status Flag ................................................. 187

INT2 and KR0 to KR1 Block Diagram ................................................................................. 202

Format of INT2 Edge Detection Mode Register (IM2) ....................................................... 203

Standby Mode Release Operation ...................................................................................... 208

The wait time when STOP mode is released ..................................................................... 210

User’s Manual U10123EJ2V1UM00

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