DSP56371 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56371

high density CMOS device with 5.0-volt compatible inputs and outputs.

Freescale Semiconductor 

DSP56371 Overview

• DSP56300 modular chassis

— 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply (QVDDL) of 1.25V.

— Object Code Compatible with the 56K core.

— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support.

— Program Control with position independent code support and instruction patch support.

— EFCOP running concurrently with the core, capable of executing 181 million filter taps per second at peak

performance.

— Six-channel DMA controller.

— Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31)

and power saving clock divider (2i: i=0 to 7). Reduces clock noise.

— Internal address tracing support and OnCE for Hardware/Software debugging.

— JTAG port.

— Very low-power CMOS design, fully static design with operating frequencies down to DC.

— STOP and WAIT low-power standby modes.

• On-chip Memory Configuration

— 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM.

— 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

— 64Kx24 Bit Program and Bootstrap ROM.

— 4Kx24 Bit Program RAM.

— PROM patching mechanism.

— Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to Program RAM resulting in

up to 44Kx24 Bit of Program RAM.

• Peripheral modules

— Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Left

justified, Right justified, Sony, AC97, network and other programmable protocols.

— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Left

justified, Right justified, Sony, AC97, network and other programmable protocols.

— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO,

support for 8, 16 and 24-bit words.

— Triple Timer module (TEC).

— 11 dedicated GPIO pins

— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and

AES/EBU digital audio formats.

— Pins of unused peripherals (except SHI) may be programmed as GPIO lines.

2.3 DSP56371 Audio Processor Architecture

This section defines the DSP56371 audio processor architecture. The audio processor is composed of the following units:

• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller,

Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is

described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication

DSP56300FM/AD.

• Phased Lock Loop and Clock Generator

• Memory modules.

• Peripheral modules. The peripheral modules are defined in the following sections.

Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the memory mode of the

chip. See Section 2.4.7 On-Chip Memory for more details about memory size.

2.4 DSP56300 Core Functional Blocks

The DSP56300 core provides the following functional blocks:

• Data arithmetic logic unit (Data ALU)

• Address generation unit (AGU)

Freescale Semiconductor

DSP56371 Technical Data

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