S25FL204K View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL204K

4-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors

Spansion Inc. 

Data Sheet (Preliminary)

CS

SC K

SI/IO0

Figure 8.1 Write Enable Command Sequence

M o d e3

M o d e0

01

2 34 5 6 7

Instruction (06 H)

M o d e3

M o d e0

SO

H igh Im pedance

8.2 Write Disable (04h)

The Write Disable command (Figure 8.2) resets the Write Enable Latch (WEL) bit to a 0, which disables the

device from accepting a write, program or erase command. The host system must first drive CS# low, write

the WRDI command, and then drive CS# high. The WEL bit is automatically reset after Power-up and upon

completion of the Write Status Register, Page Program, Sector Erase, Block Erase, and Chip Erase

commands.

CS

SC K

SI/IO0

Figure 8.2 Write Disable Command Sequence

M ode3

M ode0

01

2

34

5

6

7

Instruction (04 H)

M ode3

M ode0

SO

H igh Im pedance

8.3

Read Status Register (05h)

The Read Status Register (RDSR) command outputs the state of the Status Register bits. The RDSR

command may be written at any time, even while a program, erase, or Write Registers operation is in

progress. The host system should check the Write In Progress (WIP) bit before sending a new command to

the device if an operation is already in progress. Figure 8.3 shows the RDSR command sequence, which also

shows that it is possible to read the Status Register continuously until CS# is driven high. (See Section 6.4,

Status Register on page 12).

16

S25FL204K

S25FL204K_00_05 August 14, 2012

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