S25FL204K View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL204K

4-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors

Spansion Inc. 

Data Sheet (Preliminary)

Figure 8.7 Fast Read Dual Output Command Sequence

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

SCK Mode0

Instruction (3BH)

24-Bit Address

SI/IO0

23 22 21 3 2 1 0

*

High Impedance

SO

CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 51 53 54 55

SCK

Dummy Clocks

SI/IO 0 switches from input to output

SI/IO0

6 420 64 20 6 4 20 64 20 6

SO

*=M SB

7 531 75317 531 75317

*

D ata out 1

*

D ata out 2

*

D ata out 3

* Data out 4 *

8.8

Page Program (PP) (02h)

The Page Program command allows up to 256 bytes of data to be programmed at previously erased to all 1s

(FFh) memory locations. A Write Enable command must be executed before the device will accept the Page

Program command (Status Register bit WEL must equal 1). The command is initiated by driving the CS# pin

low then shifting the command code “02h” followed by a 24-bit address (A23-A0) and at least one data byte,

into the SI/IO0 pin. The CS# pin must be held low for the entire length of the command while data is being

sent to the device. The Page Program command sequence is shown in Figure 8.8.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)

should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page

length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial

page) can be programmed without having any effect on other bytes within the same page. One condition to

perform a partial page program is that the number of clocks can not exceed the remaining page length. If

more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and

overwrite previously sent data.

As with the write and erase commands, the CS# pin must be driven high after the eighth bit of the last byte

has been latched. If this is not done the Page Program command will not be executed. After CS# is driven

high, the self-timed Page Program command will commence for a time duration of tPP. See AC

Characteristics on page 31. While the Page Program cycle is in progress, the Read Status Register

command may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page

Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands

again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is

cleared to 0. The Page Program command will not be executed if the addressed page is protected by the

Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 13).

20

S25FL204K

S25FL204K_00_05 August 14, 2012

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