S25FL216K0PMFI04 View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL216K0PMFI04

16-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors

Spansion Inc. 

Data Sheet (Preliminary)

7.1 Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a

Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program

cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to

be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the

same page of memory.

7.2 Sector Erase, Block Erase, and Chip Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of

memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector

Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire

memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE, tBE, or tCE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

7.3 Polling During a Write, Program, or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE, or CE)

can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE, or tCE). The Write In Progress (WIP)

bit is provided in the Status Register so that the application program can monitor its value, polling it to

establish when the previous Write cycle, Program cycle or Erase cycle is complete.

7.4 Active Power, Stand-by Power, and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select

(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have

completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The

device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode

(DP) instruction) is executed, with the device consumption at ICC2. The device remains in this mode until

another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction)

is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an

extra software protection mechanism, when the device is not in active use, to protect the device from

inadvertent Write, Program or Erase instructions.

8. Commands

The command set of the S25FL216K consists of fifteen basic instructions that are fully controlled through the

SPI bus (see Table 8.1). The host system must shift all commands, addresses, and data in and out of the

device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the

device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each

successive bit is latched on the rising edge of SCK.

Every command sequence begins with a one-byte command code. The command may be followed by

address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the

command sequence has been written. All commands that write, program or erase require that CS# be driven

high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS#

must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of

eight. The device ignores any attempt to access the memory array during a Write Registers, program, or

erase operation, and continues the operation uninterrupted.

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S25FL216K

S25FL216K_00_07 August 9, 2012

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