S25FL216K0PMFI04 View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL216K0PMFI04

16-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors

Spansion Inc. 

Data Sheet (Preliminary)

Figure 8.3 Read Status Register Command Sequence

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SC K M ode0

SI/IO0

Instruction (05H )

SO

*=M SB

High Im pedance

Status Register O ut

Status Register O ut

7 6 54 3 2 1 07 6 54 3 2 1 0 7

*

*

8.4

Write Status Register (01h)

The Write Status Register command allows the Status Register to be written. A Write Enable command must

previously have been executed for the device to accept the Write Status Register command (Status Register

bit WEL must equal 1). Once write enabled, the command is entered by driving CS# low, sending the

instruction code “01h”, and then writing the status register data byte as illustrated in Figure 8.4. The Status

Register bits are shown in Table 6.1 on page 12 and described in Section 6.4, Status Register on page 12.

Only non-volatile Status Register bits SRP, BP3, BP2, BP1, and BP0 (bits 7, 5, 4, 3, and 2) can be written to.

All other Status Register bit locations are read-only and will not be affected by the Write Status Register

command.

The CS# chip select input pin must be driven to the logic high state after the eighth bit of data has been

latched in. If not, the Write Status Register command is not executed. As soon as the CS# chip select input

pin is driven to the logic high state, the self-timed Write Status Register cycle is initiated. While the Write

Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In

Progress (WIP) bit. The Write In Progress (WIP) bit is a 1 during the self-timed Write Status Register cycle,

and is a 0 when it is completed. When the Write Status Register cycle is completed, the Write Enable Latch

(WEL) is set to a 0.

The Write Status Register command allows the Block Protect bits (BP3, BP2, BP1, and BP0) to be set for

protecting all, a portion, or none of the memory from erase and program commands. Protected areas become

read-only (see Table 7.1 on page 13). The Write Status Register command also allows the Status Register

Protect bit (SRP) to be set. This bit is used in conjunction with the Write Protect (WP#) pin to disable writes to

the status register. When the SRP bit is set to a 0 state (factory default) the WP# pin has no control over the

status register. When the SRP pin is set to a 1, the Write Status Register command is locked out while the

WP# pin is low. When the WP# pin is high the Write Status Register command is allowed.

August 9, 2012 S25FL216K_00_07

S25FL216K

17

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