S5L9290X View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9290X

DIGITAL SIGNAL PROCESSOR FOR CDP

Samsung 

DIGITAL SIGNAL PROCESSOR FOR CDP

PRELIMINARY

S5L9290X

DIGITAL PLL

Essentially uses the existing digital PLL configuration while changing the frequency of the frequency synthesizer,

which suppliew the DPLL clock, according to the EFM signal bit rate to allow wide capture range PLL.

Wide capture range PLL is generated the SRAM jitter by changeing the in/output rate of SRAM buffer and can

selected the jitterfree mode to prevent the SRAM jitter.

XIN

1/P1

1/M1

VCO1O

1/S1

EFMI

FREQUENCY

DETECTOR

PLL1

DPDO1

LOOP

FILTER1

CNTVOL1

VCO1

M1

DPLL

PLCK

to

EFM demodulation

< Block Diagram >

PLL1 is the frequency synthesizer to supply the reference clock in DPLL and receives the crystal input

(16.9344MHz) to generate a clock with Xtimes of PLCK.

The next is frequency equation of frequency synthesizer and is changed the divider value automally by sekect the

times

Font = Fin × p----m-×-----s--

Fin: input frequency, Font: output frequecy

p: ore-divider (=DIVP+2), m: main-divider (DIVM+8), s: port-scalor (2DIVS)

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