45PE80 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

45PE80

Micron Serial NOR Flash Memory

Micron Technology 

75MHz, Serial Peripheral Interface Flash Memory

Command Set Overview

Command Set Overview

All commands, addresses, and data are shifted in and out of the device, most significant

bit first.

Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C)

after chip select (S#) is driven LOW. Then, the 1-byte command code must be shifted

into the device, most significant bit first, on DQ0 and DQ1, with each bit latched on the

rising edges of C.

Every command sequence starts with a 1-byte command code. Depending on the com-

mand, this command code might be followed by address or data bytes, by address and

data bytes, or by neither address nor data bytes. For the following commands, the shif-

ted-in command sequence is followed by a data-out sequence. S# can be driven HIGH

after any bit of the data-out sequence is being shifted out.

• READ DATA BYTES (READ)

• READ DATA BYTES at HIGHER SPEED

• READ STATUS REGISTER

For the following commands, S# must be driven HIGH exactly at a byte boundary. That

is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must

be driven HIGH. Otherwise, the command is rejected and not executed.

• PAGE WRITE

• PAGE PROGRAM

• PAGE ERASE

• SECTOR ERASE

• WRITE ENABLE

• WRITE DISABLE

• DEEP POWER-DOWN

• RELEASE FROM DEEP POWER-DOWN

All attempts to access the memory array are ignored during a WRITE STATUS REGIS-

TER, PROGRAM, or ERASE command cycle. In addition, the internal cycle for each of

these commands continues unaffected.

PDF: 09005aef845660e5

m45pe80.pdf - Rev. C 03/14 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2011 Micron Technology, Inc. All rights reserved.

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