BC57E687C View Datasheet(PDF) - Unspecified
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BC57E687C Datasheet PDF : 104 Pages
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Contents
List of Figures
Figure 2.1 Functional Block Diagram ............................................................................................................... 11
Figure 3.1 Device Pinout .................................................................................................................................. 12
Figure 3.2 169-ball TFBGA Package Dimensions ............................................................................................ 21
Figure 4.1 Simplified Circuit RF_N and RF_P .................................................................................................. 23
Figure 4.2 Internal Power Ramping .................................................................................................................. 24
Figure 4.3 BDR and EDR Packet Structure ..................................................................................................... 26
Figure 5.1 Clock Architecture ........................................................................................................................... 27
Figure 5.2 TCXO Clock Accuracy .................................................................................................................... 29
Figure 5.3 Crystal Driver Circuit ....................................................................................................................... 29
Figure 5.4 Crystal Equivalent Circuit ................................................................................................................ 29
Figure 6.1 Example TCXO Enable OR Function .............................................................................................. 32
Figure 7.1 Kalimba DSP Interface to Internal Functions .................................................................................. 34
Figure 8.1 Memory Write Cycle ........................................................................................................................ 38
Figure 8.2 Memory Read Cycle ........................................................................................................................ 39
Figure 9.1 Universal Asynchronous Receiver .................................................................................................. 40
Figure 9.2 Break Signal .................................................................................................................................... 41
Figure 9.3 UART Bypass Architecture ............................................................................................................. 42
Figure 9.4 Example EEPROM Connection ...................................................................................................... 44
Figure 10.1 Audio Interface ................................................................................................................................ 45
Figure 10.2 Stereo Codec Audio Input and Output Stages ................................................................................ 46
Figure 10.3 ADC Analogue Amplifier Block Diagram ......................................................................................... 48
Figure 10.4 Example Circuit for SPDIF Interface (Co-Axial) .............................................................................. 50
Figure 10.5 Example Circuit for SPDIF Interface (Optical) ................................................................................. 50
Figure 10.6 Microphone Biasing ......................................................................................................................... 50
Figure 10.7 Differential Input .............................................................................................................................. 54
Figure 10.8 Single-ended Input .......................................................................................................................... 54
Figure 10.9 Speaker Output ............................................................................................................................... 54
Figure 10.10 PCM Interface Master ..................................................................................................................... 57
Figure 10.11 PCM Interface Slave ....................................................................................................................... 57
Figure 10.12 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 57
Figure 10.13 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 58
Figure 10.14 Multi-slot Operation with Two Slots and 8-bit Companded Samples .............................................. 58
Figure 10.15 GCI Interface ................................................................................................................................... 58
Figure 10.16 16-Bit Slot Length and Sample Formats ......................................................................................... 59
Figure 10.17 PCM Master Timing Long Frame Sync ........................................................................................... 61
Figure 10.18 PCM Master Timing Short Frame Sync .......................................................................................... 61
Figure 10.19 PCM Slave Timing Long Frame Sync ............................................................................................. 62
Figure 10.20 PCM Slave Timing Short Frame Sync ............................................................................................ 63
Figure 10.21 Digital Audio Interface Modes ......................................................................................................... 67
Figure 10.22 Digital Audio Interface Slave Timing ............................................................................................... 68
Figure 10.23 Digital Audio Interface Master Timing ............................................................................................. 69
Figure 11.1 Voltage Regulator Configuration ..................................................................................................... 70
Figure 11.2 LED Equivalent Circuit .................................................................................................................... 73
Figure 12.1 Example Application Schematic ...................................................................................................... 76
Figure 16.1 BlueCore HCI Stack ........................................................................................................................ 93
Figure 18.1 Tape and Reel Orientation .............................................................................................................. 97
Figure 18.2 Tape Dimensions ............................................................................................................................ 98
Figure 18.3 Reel Dimensions ............................................................................................................................. 99
CS-121064-DSP4
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This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2006 - 2010
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