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BC57E687C View Datasheet(PDF) - Unspecified

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BC57E687C Datasheet PDF : 104 Pages
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Contents
List of Tables
Table 4.1 TXRX_PIO_CONTROL Values ........................................................................................................ 24
Table 4.2 Data Rate Schemes ......................................................................................................................... 26
Table 5.1 PS Key Values for CDMA/3G Phone TCXO .................................................................................... 27
Table 5.2 External Clock Specifications ........................................................................................................... 28
Table 5.3 Crystal Specification ......................................................................................................................... 29
Table 8.1 Flash Device Hardware Requirements ............................................................................................. 36
Table 8.2 Flash Sector Boundaries .................................................................................................................. 36
Table 8.3 Common Flash Interface Algorithm Command Set Codes .............................................................. 37
Table 8.4 Erase Block Region Information for Uniform 2KW Sectors .............................................................. 37
Table 8.5 Erase Block Region Information for Uniform 1KW Sectors .............................................................. 37
Table 8.6 Erase Block Region Information for 8 x 4KW, n x 32KW Sectors .................................................... 37
Table 8.7 Erase Block Region Information for 1 x 8KW, 2 x 4KW, 1 x 16KW, n x 32KW Sectors ................... 37
Table 8.8 Memory Write Cycle ......................................................................................................................... 38
Table 8.9 Memory Read Cycle ......................................................................................................................... 39
Table 9.1 Possible UART Settings ................................................................................................................... 40
Table 9.2 Standard Baud Rates ....................................................................................................................... 41
Table 9.3 Instruction Cycle for a SPI Transaction ............................................................................................ 43
Table 10.1 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 45
Table 10.2 ADC Digital Gain Rate Selection ...................................................................................................... 47
Table 10.3 DAC Digital Gain Rate Selection ...................................................................................................... 49
Table 10.4 DAC Analogue Gain Rate Selection ................................................................................................. 49
Table 10.5 Voltage Output Steps ....................................................................................................................... 52
Table 10.6 Current Output Steps ....................................................................................................................... 53
Table 10.7 PCM Master Timing .......................................................................................................................... 60
Table 10.8 PCM Slave Timing ............................................................................................................................ 62
Table 10.9 PSKEY_PCM_LOW_JITTER_CONFIG Description ......................................................................... 64
Table 10.10 PSKEY_PCM_CONFIG32 Description ............................................................................................. 64
Table 10.11 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 65
Table 10.12 PSKEY_DIGITAL_AUDIO_CONFIG ................................................................................................. 66
Table 10.13 Digital Audio Interface Slave Timing ................................................................................................ 68
Table 10.14 Digital Audio Interface Master Timing .............................................................................................. 69
Table 11.1 BlueCore5‑Multimedia External Voltage Regulator Enable Pins ...................................................... 72
Table 11.2 Pin States on Reset .......................................................................................................................... 74
List of Equations
Equation 4.1 Output Voltage with Load Current I ................................................................................................. 24
Equation 4.2 Output Voltage with No Load Current ............................................................................................. 24
Equation 5.1 Load Capacitance ........................................................................................................................... 30
Equation 5.2 Trim Capacitance ............................................................................................................................ 30
Equation 5.3 Frequency Trim ............................................................................................................................... 30
Equation 5.4 Pullability ......................................................................................................................................... 30
Equation 5.5 Transconductance Required for Oscillation .................................................................................... 31
Equation 5.6 Equivalent Negative Resistance ..................................................................................................... 31
Equation 9.1 Baud Rate ....................................................................................................................................... 41
Equation 10.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 56
Equation 10.2 IIR Filter plus DC Blocking Transfer Function, HDC(z) .................................................................... 56
Equation 10.3 PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock ........................... 63
CS-121064-DSP4
Production Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2006 - 2010
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