C8051F97X View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F97X Datasheet PDF : 455 Pages
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The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and
modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional while debugging.
Each device is specified for 1.8 to 3.6 V operation, and are available in 48-pin QFN, 32-pin QFN, or 24-pin QFN
packages. All package options are lead-free and RoHS compliant. The device is available in two temperature
grades: -40 to +85 °C. See Table 4.1 for ordering information. A block diagram is included in Figure 2.1.
C2CK/RST
VDD
GND
Reset
Controller
Power On
Reset
Reset
CIP-51 8051
Controller Core
16-32 kB ISP Flash
Program Memory
Debug/
Programming
Hardware
C2D
Analog
Power
VREG
Power
Management
Unit
256 Byte SRAM
4-8 kB XRAM
Digital
Power
System Clock Configuration
Low-Power 20
MHz Oscillator
Precision 24.5
MHz Oscillator
External
Oscillator Circuit
SmaRTClock
SYSCLK
PCLK[0]
Clock PCLK[1]
Gen PCLK[2]
...
PCLK[n]
Digital Peripherals
PCA/WDT
Timers 0,1,2,3
SPI
I2C / SMBus
Priority
Crossbar
Decoder
UART
High-Speed I2C Slave
Crossbar Control
SFR
Bus
Analog Peripherals
10-bit
300 ksps
ADC
VDD
Temp
Sensor
GND
VDD
VREF
Capacitance
To Digital
Converter
AMUX0
MAC
DMA
CRC
Engine
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
Figure 2.1. C8051F97x Family Block Diagram (QFN-48 Shown)
P0.0/VREF
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL3/CNVSTR
P0.7/XTAL4
P1.0/XTAL1
P1.1/XTAL2
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4,2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P6.0/SCL
P6.1/SDA
23
Rev 1.1
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