C8051F97X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F97X

Low Power Capacitive Sensing MCU with up to 32 kB of Flash

Silicon Laboratories 

DOCUMENT CHANGE LIST

Revision 1.0 to Revision 1.1

Updated packaging information for QFN48 and QFN32 packages in "5. QFN-48 Package Specifications"

on page 43 and "6. QFN-32 Package Specifications" on page 46.

Added a note about an additional divide-by-2 stage on RC and C oscillator modes in "24.3.2. External RC

Mode" on page 243 and "24.3.3. External Capacitor Mode" on page 245.

Fixed the first sentence in "26.3. Priority Crossbar Decoder" on page 281 that referred to UART0 as the top

priority peripheral on the crossbar.

Removed all ADC0MX channels other than ADC0.0 and marked them as Reserved, since pin selections

are made using AMUX0.

Updated Table 3.1, “Pin Definitions for C8051F970/3-A-GM (QFN-48),” on page 32, Table 3.2, “Pin

Definitions for C8051F971/4-A-GM (QFN-32),” on page 36, and Table 3.3, “Pin Definitions for C8051F972/

5-A-GM (QFN-24),” on page 39 to replace ADC0.n with AMUX0.n.

Updated QFN-32 and QFN-24 pin definitions with correct pin numbering.

Added wake-up request and RTC oscillator output to Table 3.1, “Pin Definitions for C8051F970/3-A-GM

(QFN-48),” on page 32 and specified in Register 16.4, “PMU0MD: Power Management Unit Mode,” on

page 103 that these outputs are not available on QFN-32 and QFN-24 packages.

Removed a mention of UART0 routing to P0.4 and P0.5 in Register 26.1, “XBR0: Port I/O Crossbar 0,” on

page 285.

Updated Figure 22.4, “DMA Mode Operation Flow Chart,” on page 206 to remove clearing ACCMD to 0

and added a note in "22.6. DMA Mode Operation" on page 205 regarding generating the MAC output for

two arrays.

Updated all references of “QFN-28” to “QFN-24.”

Added a note to "16.5. Sleep Mode" on page 97 that entering Sleep mode may cause a device to

disconnect while debugging.

Updated the PERIPH field in Register 21.6, “DMA0NCF: DMA0 Channel Configuration,” on page 195 to

swap values 6 and 7.

Updated references to MSTEN to refer to SPI0CFG instead of SPI0CN in "28. Serial Peripheral Interface

(SPI0)" on page 328.

Updated the example in "22.11.3. Initializing Memory Block Using DMA0 and MAC0" on page 212 to refer

to the MAC0ITER register instead of MAC0ICT.

Removed section 24.4.2 SMBus Pin Swap and 29.4.3 SMBus Timing Control because these features are

not available on this device family.

Revision 0.1 to Revision 1.0

Updated Capacitive Sense and ADC input channels listed on the front page.

Removed mention of the -I temperature grade from Figure 4.1, “C8051F97x Part Numbering,” on page 41.

Updated Digital Supply Current numbers in Table 1.2, “Global Electrical Characteristics,” on page 10 to

reflect the latest data.

Removed mention of 12-bit mode for ADC0.

Added a note to "17.1. ADC0 Analog Multiplexer" on page 105, the ADC0MX register, and all AMUX0

registers regarding disconnecting the AMUX0 when measuring an internal signal with the ADC.

Updated "24. Clocking Sources" on page 241 to mention that the external oscillator is not available on

QFN-24 (C8051F972/5) packages.

Updated "25. SmaRTClock (Real Time Clock, RTC0)" on page 253 references to RTC0CN at address 0x05

to correctly refer to RTC0XCN.

Updated "25. SmaRTClock (Real Time Clock, RTC0)" on page 253 to remove mention of using an external

CMOS clock with the SmaRTClock.

Updated port pins associated with the crystal pins on each package in Table 26.1, “Port I/O Assignment for

Rev 1.1

453

Share Link: