34709 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
34709 Datasheet PDF : 142 Pages
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Functional Block Description
7 Functional Block Description
7.1 Start-up Requirements
At power-up, switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps, to limit the inrush current after
an initial delay of 8.0 ms, in which the core circuitry gets enabled. To ensure a proper power-up sequence, the outputs of the
switching regulators that are not enabled, are discharged at the beginning of the Cold start with weak pull-downs on the output.
For that same reason, an 8.0 ms delay allows the outputs of the linear regulators to be fully discharged as well, through the built
in discharge path. The peak inrush current per event is limited. Any under-voltage detection at BP is masked while the power-up
sequencer is running. When the switching regulator is enabled, it will start in PWM mode for 3.0 ms. Then it will switch over to
the mode that it is programmed to in the SPI.
The Power-up Mode Select pins PUMSx (x = 1,2,3,4,5) are used to configure the start-up characteristics of the regulators. Supply
enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. The recommended
power-up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the
bare essentials to allow processor start-up and software to run. With such a strategy, the start-up transients are controlled at
lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering,
where specific sequences may be required, as well as supply default values. Software code can load up all of the required
programmable options, to avoid sneak paths, under/over-voltage issues, start-up surges, etc, without any change in hardware.
The state of the PUMSx pins are latched in before any of the switching or linear regulators are enabled, with the exception of
VCORE. PUMSx options and start-up configurations will be robust to a PCUT event, whether occurring during normal operation
or during the 8.0 ms of pre-sequencer initialization, i.e., the system will not end up in an unexpected / undesirable consumption
state.
Table 9 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled.
Table 9. Power-up Defaults
i.MX
Reserved
53
LPM
53
53
53
DDR2 DDR3 LVDDR3
PUMS[4:1] 0000-0100
0101
0110
0111
1000
PUMS5=0
VUSB2
VGEN2
Reserved
Ext PNP Ext PNP Ext PNP Ext PNP
PUMS5=1
VUSB2
VGEN2
Reserved
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
SW1A
(VDDGP)
Reserved
1.1
1.1
1.1
1.1
SW1B
(VDDGP)
Reserved
1.1
1.1
1.1
1.1
SW2(28)
(VCC)
Reserved
1.225
1.3
1.3
1.3
SW3(28)
(VDDA)
Reserved
1.2
1.3
1.2
1.2
SW4A(28)
(DDR/SYS)
Reserved
1.5
1.8
1.5
1.35
SW4B(28)
(DDR/SYS)
Reserved
1.5
1.8
1.5
1.35
SW5(28)
(I/O)
Reserved
1.8
1.8
1.8
1.8
SWBST
Reserved
Off
Off
Off
Off
53
LVDDR2
1001
50
1010
50
1011
50
1100
50
1101
50
1110
50
1111
Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP
Internal
PMOS
Internal
PMOS
Internal Internal Internal Internal Internal
PMOS PMOS PMOS PMOS PMOS
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.3
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.8
1.2
3.15
3.15
3.15
3.15
1.2
1.8
1.2
1.2
1.8
1.2
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
Off
Off
Off
Off
Off
Off
Off
Analog Integrated Circuit Device Data
Freescale Semiconductor
34709
20
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