56F8357 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

56F8357

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Power Distribution and I/O Ring Implementation

• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins

• Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as

development or debugging systems) should allow a means to assert TRST whenever RESET is

asserted, as well as a means to assert TRST independently of RESET. Designs that do not require

debugging functionality, such as consumer products, should tie these pins together.

• Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should

provide an interface to this port to allow in-circuit Flash programming

12.3 Power Distribution and I/O Ring Implementation

Figure 12-1 illustrates the general power control incorporated in the 56F8357. This chip contains

an internal regulator which cannot be disabled. The regulator takes regulated 3.3V power from the

VDD_IO pins and provides 2.5V to the internal logic of the chip. This means the entire part is

powered from the 3.3V supply.

Notes:

• Flash, RAM and internal logic are powered from the core regulator output

• VPP1 and VPP2 are not connected in the customer system

• All circuitry, analog and digital, shares a common VSS bus

VDDA_OSC_PLL

VDD

VDDA_ADC

OCS

REG

ROSC

REG

VCAP

I/O

CORE

ADC

VREFH

VREFP

VREFMID

VREFN

VREFLO

VSS

Figure 12-1 56F8357 Power Management

VSSA_ADC

56F8357 Technical Data

155

Preliminary

For More Information On This Product,

Go to: www.freescale.com

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