56F802 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F802 Datasheet PDF : 40 Pages
| |||
2.3 Interrupt and Program Control Signals
Interrupt and Program Control Signals
No. of
Pins
1
Signal
Name
RESET
Table 2-5 Program Control Signals
Signal State During
Type
Reset
Signal Description
Input
(Schmitt)
Input
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
2.4 Pulse Width Modulator (PWM) Signals
Table 2-6 Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6 PWMA0-5 Output
Tri-stated PWMA0-5— These are six PWMA output pins.
1 FAULTA0 Input
(Schmitt)
Input
FAULTA0 —This fault input is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
2.5 Serial Communications Interface (SCI) Signals
Table 2-7 Serial Communications Interface (SCI0) Signals
No. of
Pins
1
Signal
Name
TXD0
Signal
Type
Output
State During
Reset
Input
Signal Description
Transmit Data (TXD0)—SCI0 transmit data output
GPIOB0 Input/Ou
tput
Input
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.
After reset, the default state is SCI output.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
11
Share Link: 