56F803 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F803 Datasheet PDF : 52 Pages
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No. of
Pins
16
Signal
Name
D0–D15
Signal
Type
Input/O
utput
Table 2-7 Data Bus Signals
State During
Reset
Signal Description
Tri-stated
Data Bus— D0–D15 specify the data for external Program or Data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pull-ups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
1
1
1
1
Signal Signal State During
Name Type
Reset
Signal Description
PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory
access.
DS Output Tri-stated Data Memory Select—DS is asserted low for external Data memory access.
WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data
on the bus. When WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0–A15, PS, and
DS pins. WR can be connected directly to the WE pin of a Static RAM.
RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the controller. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
2.5 Interrupt and Program Control Signals
No. of
Pins
1
1
Signal
Name
IRQA
IRQB
Table 2-9 Interrupt and Program Control Signals
Signal
Type
Input
(Schmitt)
Input
(Schmitt)
State During
Reset
Signal Description
Input
Input
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge- triggered.
External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
56F803 Technical Data, Rev. 16
12
Freescale Semiconductor
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