DSP56853 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56853 Datasheet PDF : 60 Pages
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Introduction
Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
73
86
87
88
89
90
107
108
109
110
111
122
123
126
127
128
7
Signal Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RD
Type
Description
Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for
external program or data memory accesses.
Output
Read Enable (RD) —is asserted during external memory read cycles.
8
WR
Output
This signal is pulled high during reset.
Write Enable (WR)— is asserted during external memory write
cycles.
75
CS0
Output
This signal is pulled high during reset.
External Chip Select (CS0)—This pin is used as a dedicated GPIO.
GPIOA0
Input/Output
Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
76
CS1
Output
External Chip Select (CS1)—This pin is used as a dedicated GPIO.
GPIOA1
Input/Output
Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
77
CS2
Output
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
GPIOA2
Input/Output
Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
78
CS3
Output
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
GPIOA3
Input/Output
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
56853 Technical Data, Rev. 6
Freescale Semiconductor
13
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