Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
77
CS2
Output
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
GPIOA2
Input/Output
Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
78
CS3
Output
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
GPIOA3
Input/Output
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
30
HD0
Input
Host Address (HD0)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
GPIOB0
Input/Output
Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
31
HD1
Input
Host Address (HD1)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
GPIOB1
Input/Output
Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
32
HD2
Input
Host Address (HD2)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
GPIOB2
Input/Output
Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
36
HD3
Input
Host Address (HD3)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
GPIOB3
Input/Output
Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
37
HD4
Input
Host Address (HD4)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
GPIOB4
Input/Output
Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
56854 Technical Data, Rev. 6
14
Freescale Semiconductor