DSP56854 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56854

16-bit Digital Signal Controllers

Freescale Semiconductor 

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No.

Signal Name

Type

Description

121

SC02

Input/Output ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync

I/O. SC02 is the frame sync for both the transmitter and receiver in

synchronous mode and for the transmitter only in asynchronous

mode. When configured as an output, this pin is the internally

generated frame sync signal. When configured as an input, this pin

receives an external frame sync signal for the transmitter (and the

receiver in synchronous operation).

GPIOC5

Input /Output

Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin

when the ESSI is not in use.

1

MISO

Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to

a master device and an output from a slave device. The MISO line

of a slave device is placed in the high-impedance state if the slave

device is not selected. The driver on this pin can be configured as

an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when

this pin is configured for SPI operation.

GPIOF0

Input/Output

Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as input or output pin.

2

MOSI

Input/Output (Z) SPI Master Out/Slave In (MOSI)—This serial data pin is an output

from a master device and an input to a slave device. The master

device places data on the MOSI line a half-cycle before the clock

edge that the slave device uses to latch the data. The driver on this

pin can be configured as an open-drain driver by the SPI’s WOM bit

when this pin is configured for SPI operation.

GPIOF1

Input/Output

Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

3

SCK

Input/Output SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit

rate clock for the SPI. This gated clock signal is an input to a slave

device and is generated as an output by a master device. Slave

devices ignore the SCK signal unless the SS pin is active low. In

both master and slave SPI devices, data is shifted on one edge of

the SCK signal and is sampled on the opposite edge, where data is

stable. The driver on this pin can be configured as an open-drain

driver by the SPI’s WOM bit when this pin is configured for SPI

operation. When using Wired-OR mode, the user must provide an

external pull-up device.

GPIOF2

Input/Output

Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as input or output pin.

56854 Technical Data, Rev. 6

20

Freescale Semiconductor

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