81C55 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
81C55 Datasheet PDF : 19 Pages
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¡ Semiconductor
MSM81C55-5RS/GS/JS
(2) Reading the C/S Register
The I/O and timer status can be accessed by reading the contents of the Status register
located at I/O address xxxxx000. The status word format is shown below:
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
TIMER
INTE
B
B
BF
INTR INTE
B
A
A
BF
INTR
A
Port A Interrupt Request
Port A Buffer Full
Port A Interrupt Enable
Port B Interrupt Request
Port B Buffer Full
Port B Interrupt Enable
Timer Interrupt. This bit is set high when the timer
reaches TC, and is reset when the C/S register is read
or a hardware reset occurs.
(3) PA and PB Registers
These registers may be used as either input or output ports depending on the programmed
contents of the C/S register. They may also be used either in the basic mode or in the strobe
mode.
I/O address of the PA register: xxxxx001
I/O address of the PB register: xxxxx010
(4) PC Register
The PC register may be used as an input port, output port or control register depending on
the programmed contents of the C/S register. The I/O address of the PC register is
xxxxx011.
(5) Timer
The timer is a 14-bit down counter which counts TIMER IN pulses.
The low order byte of the timer register has an I/O address of xxxxx100, and the high order
byte of the register has an I/O address of xxxxx101.
The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are
assigned to the count length and bits 14 and 15 specify the timer output mode. A read
operation of the CLR reads the contents of the counter and the pertinent output mode. The
initial value range which can initially be loaded into the counter is 2 through 3FFF hex. Bit
assignments to the timer counter and possible output modes are shown in the following.
M2
M1
T13 T12 T11 T10
T9
T8
Output Mode
High Order 6 Bits of Count Length
T7
T6
T5
T4
T3
T2
T1
T0
Low Order Byte of Count Length
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