A8351601 View Datasheet(PDF) - AMIC Technology
Part Name
Description
Manufacturer
A8351601 Datasheet PDF : 44 Pages
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A8351601 Series
T2CON: (continued)
7
6
TF2
EXF2
Register Description:
EXEN2
T2CON.3
TR2
C/ T2
CP/ RL2
T2CON.2
T2CON.1
T2CON.0
Notes:
Timer 2 Operating Modes
RCLK + TCLK
0
0
1
CP/ RL2
0
1
X
5
4
3
2
RCLK
TCLK
EXEN2
TR2
1
C/ T2
0
CP/ RL2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
Software START/STOP control for Timer 2. A logic 1 starts the Timer.
Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling
edge).
Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2
=1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions
at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the Timer
is forced to auto-reload on Timer 2 overflow.
TR2
MODE
1
16-Bit Auto-Reload
1
16-Bit Capture
1
Baud Rate Generator
ADD(A1H):
Extra Additional Register. Not Bit Addressable.
7
6
5
4
3
2
1
0
-
-
Delay2
Delay1
Delay0
T2EXREV
DF
RAMDIS
Register Description:
-
Not implemented, reserve for future use.
-
Not implemented, reserve for future use.
D2
PWM3 delay control bit.
D1
PWM3 delay control bit.
D0
PWM3 delay control bit.
T2EXREV T2EX reverse control bit. Set/Cleared by software specify T2EX pin reverse/no reverse.
DF
Double system frequency control bit. Set/Cleared by software specify Xtal frequency *2 / Xtal frequency.
RAMDIS
Build in 8K bytes SRAM enable/disable control bit. Set/Cleared by software specify
Enable/disable build in 8K bytes SRAM.
Bit <5:3>
Delay
0
4 CLK
1
5 CLK
2
6 CLK
3
7 CLK
(D2, D1, D0) controlled the delay time of PWM3 after PWM1 change.
4
8 CLK
5
9 CLK
6
10 CLK
7
11 CLK
(July, 2002, Version 1.0)
11
AMIC Technology, Inc.
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