AD1836A View Datasheet(PDF) - Analog Devices
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AD1836A Datasheet PDF : 24 Pages
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SPI CONTROL REGISTERS
Note that all control registers default to zero at power-up.
Table 12. Serial SPI Word Format
Register Address
15:12
4 Bits
Read/Write
11
1 = Read
0 = Write
Reserved
10
0
AD1836A
Data Field
9:0
10 Bits
Table 13. Register Addresses and Functions
Register Address
Bit 15
Bit 14
Bit 13
Bit 12
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
RD/WR
Bit 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Bit 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Bits 9:0
DAC Control 1
DAC Control 2
DAC1L Volume
DAC1R Volume
DAC2L Volume
DAC2R Volume
DAC3L Volume
DAC3R Volume
ADC1L—Peak Level (Read-Only)
ADC1R—Peak Level (Read-Only)
ADC2L—Peak Level (Read-Only)
ADC2R—Peak Level (Read-Only)
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
Table 14. DAC Control Register 1
Packed Mode: Eight channels are “packed” in DSDATA1 serial input. Packed Mode 128: Refer to Figure 7. Packed Mode 256: Refer to Figure 8.
Address
15, 14, 13, 12
0000
RD/WR
11
0
Reserved
10
0
Function
De-emphasis
9, 8
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
Serial Mode
7, 6, 5
000 = I2S
001 = RJ
010 = DSP
011 = LJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Reserved
111 = Reserved
Data-Word
Width
4, 3
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Power-Down
2
0 = Normal
1 = PWRDWN
Interpolator
Mode
1
0 = 8× (48 kHz)
1 = 4× (96 kHz)
Reserved
0
0
Rev. 0 | Page 19 of 24
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