AD5100(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5100
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5100 Datasheet PDF : 36 Pages
| |||
AD5100
TIMING SPECIFICATIONS
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS1, 2
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Description
SCL clock frequency
tBUF, bus free time between start and stop
tHD;STA, hold time after (repeated) start condition; after this
period, the first clock is generated
tLOW, low period of SCL clock
tHIGH, high period of SCL clock
tSU;STA, setup time for start condition
tHD;DAT, data hold time
tSU;DAT, data setup time
tF, fall time of both SDA and SCL signals
tR, rise time of both SDA and SCL signals
tSU;STO, setup time for stop condition
1 Guaranteed by design and not subject to production test.
2 See Figure 2.
t8
t6 t9
t2
SCL
t2
t3
t4
t7
t5
t8
t9
SDA
t1
P
S
S
Figure 2. Digital Interface Timing Diagram
Min Typ Max Unit
400 kHz
1.3
μs
0.6
μs
1.3
μs
0.6
50 μs
0.6
μs
0.9 μs
0.1
μs
0.3 μs
0.3 μs
0.6
μs
t10
P
Rev. 0 | Page 7 of 36
Share Link: