AD9139(Rev0) View Datasheet(PDF) - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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AD9139
Data Sheet
FIFO OPERATION
The AD9139 adopts source synchronous clocking in the data
receiver (see the Data Interface section). The nature of source
synchronous clocking is the creation of a separate clock domain
at the receiving device. In the DAC, it is the DAC clock domain,
that is, the DACCLK. Therefore, there are two clock domains
inside of the DAC: the DCI and the DACCLK. Often, these two
clock domains are not synchronous, requiring an additional
stage to adjust the timing for proper data transfer. In the
AD9139, a FIFO stage is inserted between the DCI and DACCLK
domains to transfer the received data into the core clock
domain (DACCLK) of the DAC.
The AD9139 contains a 2-channel, 16-bit wide, eight-word deep
FIFO. The FIFO acts as a buffer that absorbs timing variations
between the two clock domains. The timing budget between the
two clock domains in the system is significantly relaxed due to
the depth of the FIFO.
Figure 34 shows the block diagram of the datapath through the
FIFO. The input data is latched into the device, formatted, and
then written into the FIFO register, which is determined by the
FIFO write pointer. The value of the write pointer is incremented
every time a new word is loaded into the FIFO. Meanwhile, data
is read from the FIFO register, which is determined by the read
pointer, and fed into the digital datapath. The value of the read
pointer is incremented every time data is read into the datapath
from the FIFO. The FIFO pointers are incremented at the data
rate, which is the DACCLK rate divided by the interpolation rate.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow (full) or underflow (empty). An overflow or
underflow condition occurs when the write pointer and read
pointer point to the same FIFO slot. This simultaneous access of
data leads to unreliable data transfer through the FIFO and must be
avoided.
Normally, data is written to and read from the FIFO at the same
rate to maintain a constant FIFO depth. If data is written to the
FIFO faster than data is read, the FIFO depth increases. If data
is read from the FIFO faster than data is written to it, the FIFO
depth decreases. For optimal timing margin, maintain the FIFO
depth near half full (a difference of four between the write
pointer and read pointer values). The FIFO depth represents the
FIFO pipeline delay and is part of the overall latency of the
AD9139.
FIFO WRITE CLOCK
FIFO READ CLOCK
FIFO
÷INT
DACCLK
FIFO SLOT 0
DCI
RETIMED DCI
FIFO SLOT 1
FIFO SLOT 2
READ POINTER
INPUT DATA[15:0]
DATA
RECEIVER
LATCHED
DATA[15:0]
DATA
FORMAT
[15:0]
FIFO SLOT 3
FIFO SLOT 4
FIFO SLOT 5
[15:0]
[15:0]
DATA PATH
DAC
FRAME
SPI FIFO RESET
REG 0x25[0]
WRITE
POINTER
FIFO SLOT 6
FIFO SLOT 7
RESET
LOGIC
FIFO LEVEL
FIFO LEVEL REQUEST
REG 0x23
Figure 34. Block Diagram of FIFO
Rev. 0 | Page 24 of 56
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