AD9139(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9139 Datasheet PDF : 56 Pages
| |||
Data Sheet
AD9139
MULTIDEVICE SYNCHRONIZATION AND FIXED LATENCY
A DAC introduces a variation of pipeline latency to a system.
The latency variation causes the phase of a DAC output to vary
from power-on to power-on. Therefore, the output from
different DAC devices may not be perfectly aligned even with
well aligned clocks and digital inputs. The skew between
multiple DAC outputs varies from power-on to power-on.
In applications such as transmit diversity or digital predistortion,
where deterministic latency is desired, the variation of the
pipeline latency must be minimized. Deterministic latency in
this data sheet is defined as a fixed time delay from the digital
input to the analog output in a DAC from power-on to power-on.
Multiple DAC devices are considered synchronized to each other
when each DAC in this group has the same constant latency
from power-on to power-on. Three conditions must be
identical in all of the ready-to-sync devices before these devices
are considered synchronized:
The phase of DAC internal clocks
The FIFO level
The alignment of the input data
VERY SMALL INHERENT LATENCY VARIATION
The innovative architecture of the AD9139 minimizes the
inherent latency variation. The worst-case variation in the
AD9139 is two DAC clock cycles. For example, in the case of a
1.6 GHz sample rate, the variation is less than 1.25 ns in any
scenario. Therefore, without turning on the synchronization
engine, the DAC outputs from multiple AD9139 devices are
guaranteed to be aligned within two DAC clock cycles, regardless
of the timing between the DCI and the DACCLK. No additional
clocks are required to achieve this accuracy. The user must reset
the FIFO in each DAC device through the SPI at startup.
Therefore, the AD9139 can decrease the complexity of system
design in multiple transmit channel applications.
Note the alignment of the DCI signals in the design. The DCI
signal is used as a reference in the AD9139 design to align the
FIFO and the phase of internal clocks in multiple parts. The
achieved DAC output alignment depends on how well the DCI
signals are aligned at the input of each device. The following
equation is the expression of the worst-case DAC output
alignment accuracy in the case of DCI signal mismatches:
tSK (OUT) = tSK (DCI) + 2/fDAC
where:
tSK (OUT) is the worst-case skew between the DAC outputs from
two AD9139 devices.
tSK (DCI) is the skew between two DCI signals at the DCI input of
the two AD9139 devices.
fDAC is the DACCLK frequency.
The better the alignment of the DCI signals, the smaller the
overall skew between the two DAC outputs.
FURTHER REDUCING THE LATENCY VARIATION
For applications that require finer synchronization accuracy
(DAC latency variation < 2 DAC clock cycles), the AD9139 has
a provision for enabling multiple devices to be synchronized to
each other within a single DAC clock cycle.
To reduce further the latency variation in the DAC, the
synchronization machine must be turned on and two external
clocks (frame and sync) must be generated in the system and
fed to all the DAC devices.
Setup and Hold Timing Requirement
The sync clock (SYNCCLK) serves as a reference clock in the
system to reset the clock generation circuitry in multiple AD9139
devices simultaneously. Inside the DAC, the sync clock is sampled
by the DACCLK to generate a reference point for aligning the
internal clocks; consequently, there is a setup and hold timing
requirement between the sync clock and the DAC clock.
Adopting the continuous frame reset mode (where the FIFO
and sync engine periodically reset) demands meeting the timing
requirements between the sync clock and the DAC clock;
otherwise, the device can lose lock and corrupt the output. In
the one shot frame reset mode, it is still recommended that this
timing be met at the time when the sync routine is run because
not meeting the timing can degrade the sync alignment
accuracy by one DAC clock cycle, as shown in Table 18.
The AD9139 also provides a mode by which to synchronize the
device in a one shot manner and to continue to monitor the
synchronization status. It provides a continuous sync and frame
clock to synchronize the device once and ignore the clock cycles
after detecting the first valid frame pulse. In this way, the user can
monitor the sync status without periodically resynchronizing the
device; to engage one shot sync mode, set Register 0x22[2] to 0.
Table 18. Sync Clock and DAC Clock Setup and Hold Times
Falling Edge Sync Timing (Default)
Min (ps)
tS (ns)
324
tH (ns)1
−92
|tS + tH| (ns)
232
1 The negative sign indicates the direction of the setup time. The setup time is
defined as positive when it is on the left side of the clock edge and negative
when it is on the right side of the clock edge.
SYNCHRONIZATION IMPLEMENTATION
The AD9139 allows the user to choose either the rising or
falling edge of the DAC clock to sample the sync clock, which
makes it easier to meet the timing requirements. Ensure that the
sync clock, fSYNC, is 1/8 × fDCI or slower by a factor of 2n, n being
an integer (1, 2, 3…). Note that there is a limit on how slow the
sync clock can be because of the ac coupling nature of the sync
clock receiver. Choose an appropriate value of the ac coupling
capacitors to ensure that the signal swing meets the data sheet
specification, as listed in Table 2.
Rev. 0 | Page 29 of 56
Share Link: 