AD9845B(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9845B Datasheet PDF : 24 Pages
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AD9845B
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Name
Address
A0 A1 A2 D0 D1 D2 D3 D4
Data Bits
D5
D6
Operation
0 0 0 Channel Select Power-Down Software OB Clamp
01
CCD/AUX1/2 Modes
Reset On/Off
VGA Gain 1 0 0 LSB
Clamp Level 0 1 0 LSB
Control
1 10
Color Steering Mode PxGA Clock Polarity Select for
Selection
On/Off SHP/SHD/CLP/DATA
PxGA Gain0 0 0 1 LSB
MSB
X
PxGA Gain1 1 0 1 LSB
MSB
X
PxGA Gain2 0 1 1 LSB
MSB
X
PxGA Gain3 1 1 1 LSB
MSB
X
NOTES
1Internal use only. Must be set to 0.
2Must be set to 1.
SDATA
tDS
SCK
RNW
0
A0
TEST BIT
A1 A2
0
D0 D1
tDH
D2 D3 D4
D5 D6 D7
tLS
SL
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT-WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
D7 D8
12
01
MSB X
01
01
X
X
X
X
X
X
X
X
D8 D9 D10
tLH
D9
D10
01
01
MSB X
X
X
Three- X
State
X
X
X
X
X
X
X
X
SDATA
RNW
TEST BIT
1
A0
A1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
tDH
tDV
SCK
tLS
tLH
SL
NOTES
1. RNW = READ-NOT-WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE AND IS UPDATED ON
SCK FALLING EDGES.
Figure 22. Serial Readback Operation
–14–
REV. A
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