ADSP-21366BBCZ-1AA View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10. Note that during power-up, when the VDDINT power

supply comes up after VDDEXT, a leakage current of the order of

three-state leakage current pull-up, pull-down, may be observed

on any pin, even if that is an input only (for example the RESET

pin) until the VDDINT rail has powered up.

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

tRSTVDD

RESET Low Before VDDINT/VDDEXT On

0

ns

tIVDDEVDD

tCLKVDD1

tCLKRST

VDDINT On Before VDDEXT

CLKIN Valid After VDDINT/VDDEXT Valid

CLKIN Valid Before RESET Deasserted

–50

+200

ms

0

200

ms

102

μs

tPLLRST

PLL Control Setup Before RESET Deasserted

20

μs

Switching Characteristic

tCORERST

Core Reset Deasserted After RESET Deasserted

4096tCK + 2 tCCLK 3, 4

1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,

depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate

default states at all I/O pins.

4 The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles

maximum.

RESET

tRSTVDD

VDDINT

VDDEXT

CLKIN

CLK_CFG1–0

RESETOUT

tIVDDEVDD

tCLKVDD

tCLKRST

tPLLRST

tCORERST

Figure 6. Power-Up Sequencing

Rev. G | Page 17 of 56 | March 2011

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