AHA4011C View Datasheet(PDF) - Unspecified
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AHA4011C Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
The AHA4011C is a single chip integrated
circuit that implements a high speed Reed-Solomon
Forward Error Correction algorithm. The
AHA4011C is a member of the AHA PerFEC™
family of high speed forward error correction (FEC)
devices conforming to the Intelsat IESS-308
specification.
The device supports several programmable
parameters, including, block size, error threshold,
number of check bytes, order of output and mode of
operations. Shortened blocks are supported without
requirement of zero padding typically required in
Reed Solomon decoders. The data input port is used
to initialize the programmable parameters and the
two on-chip buffers are used to input and output
data. Discontinuities in data flow may be controlled
by dedicated control pins.
High operating frequency, input and output data
rate flexibility, low processing latency and various
programmable parameters make this device ideal
for many applications including: DTV, DBS,
ADSL, Satellite Communications, ISDN, High
Performance Modems and networks.
This specification provides full electrical and
mechanical information to help a system engineer
develop a system using AHA4011C. This
document contains descriptions on correction
terms, pinout, functions and features, DC and AC
characteristics, package and mechanical
specifications, ordering information and Related
Technical Publications. Software simulation of the
RS code as implemented in the device is also
available. Please contact AHA or its authorized
sales representatives worldwide for copies of
Related Technical Publications and software
simulation.
1.1 FEATURES
HIGH PERFORMANCE
• Polynomial complies to Intelsat IESS-308;
RTCA DO-217 Appendix F, Revision D and
proposed ITU-TS SG-18 (Formerly CCITT SG-
18) standards
• 40 MBytes/sec burst transfer rate with a 40 MHz
clock for all block lengths
• Maximum channel rate of 10 MBytes/sec
continuous for block lengths from 54 bytes through
255 bytes using a 40 MHz clock
• Processing latency time less than 15.2 µsec in
continuous operation for block lengths of 100
bytes
FLEXIBILITY
• Programmable to correct from 1 to 10 error bytes
or 20 erasure bytes per block
• Block lengths programmable from 3 to 255 bytes
• Encode, decode or pass-through capability in-
line with data flow
• Outputs corrected data or correction vectors in
forward or reverse order
• Continuous or burst data transfer
• Programmable error threshold to help determine
channel performance
SYSTEM INTERFACE
• Byte wide synchronous I/O ports with internal
buffering on both ports
• Dedicated control pins permit discontinuities in
system data flow
OTHERS
• 44 pin PLCC; 50 mil lead pitch
• Pin and plug compatible with lower performance
AHA4012B
• Software emulation of the algorithm available
1.2 CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Certain signals are logically true at a voltage
defined as “low” in the data sheet. All such signals
have an “N” appended to the end of the signal
name. For example, RSTN and DSON.
– “Signal assertion” means the output signal is
logically true.
– Hex values are defined with a prefix of “0x”, such
as “0x10”.
– A range of signal names is denoted by a set of
colons between the numbers. Most significant bit
is always shown first, followed by least significant
bit. For example, DI[7:0] represents Data Input
Bus 7 through 0.
– A product of two variables is expressed with an
“×”, for example, N × Ci represents Codeword
Length multiplied by Input clocks/byte.
– Mega Bytes per second is referred to as
MBytes/sec or MB/sec.
– Channel Rate is defined as transfer rate including
user data and error correction check bytes.
PS4011C-0200
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