GVT71256D36T-4.4 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
GVT71256D36T-4.4 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
Switching Characteristics Over the Operating Range[24]
Parameter
Description
Clock
tKC
Clock Cycle Time
tKH
Clock HIGH Time
tKL
Clock LOW Time
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
VCCQ = 2.5V
tKQX
tKQLZ
tKQHZ
tOEQ
Clock to Output Invalid
Clock to Output in Low-Z[15, 25, 26]
Clock to Output in High-Z[15, 25, 26]
OE to Output Valid[27]
VCCQ = 3.3V
tOELZ
tOEHZ
VCCQ = 2.5V
OE to Output in Low-Z[15, 25, 26]
OE to Output in High-Z[15, 25, 26]
Set-up Times
tS
Address, Controls, and Data In[28]
Hold Times
tH
Address, Controls, and Data In[28]
-4.4
225 MHz
Min. Max.
4.4
1.7
1.7
2.5
3.0
1.25
0
1.25 3.0
2.5
3.0
0
2.5
1.5
0.5
-5
200 MHz
Min. Max.
5.0
2.0
2.0
3.0
3.5
1.25
0
1.25 3.0
3.0
3.5
0
2.5
1.5
0.5
-6
166 MHz
Min. Max.
6.0
2.4
2.4
3.5
4.0
1.25
0
1.25 4.0
3.5
4.0
0
3.5
1.5
0.5
-6.7
150 MHz
Min. Max.
6.7
2.6
2.6
3.5
4.5
1.25
0
1.25 4.0
3.5
4.5
0
3.5
2.0
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typical Output Buffer Characteristics
Output High Voltage
Pull-Up Current
Output Low Voltage
Pull-Down Current
VOH (V)
IOH (mA) Min. IOH (mA) Max.
VOL (V)
IOL (mA) Min. IOL (mA) Max.
–0.5
–38
–105
–0.5
0
0
0
–38
–105
0
0
0
0.8
–38
–105
0.4
10
20
1.25
–26
–83
0.8
20
40
1.5
–20
–70
1.25
31
63
2.3
0
–30
1.6
40
80
2.7
0
–10
2.8
40
80
2.9
0
0
3.2
40
80
3.4
0
0
3.4
40
80
Notes:
24. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
25. Output loading is specified with CL=5 pF as in part (a) of AC Test Loads.
26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
27. OE is a “Don’t Care” when a byte write enable is sampled LOW.
28. This is a synchronous device. All synchronous inputs must meet specified set up and hold time, except for “Don’t Care” as defined in the truth table.
20
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