AT89S8253-24SC View Datasheet(PDF) - Atmel Corporation
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AT89S8253-24SC Datasheet PDF : 59 Pages
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8. Programmable Watchdog Timer
The programmable Watchdog Timer (WDT) counts instruction cycles. The prescaler bits, PS0,
PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to
2048K instruction cycles. The available timer periods are shown in Table 8-1. The WDT time-out
period is dependent upon the external clock frequency.
The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out
without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See
Table 8-1 for the WDT period selections.
Table 8-1. Watchdog Timer Time-out Period Selection
WDT Prescaler Bits
PS2
PS1
PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Period (Nominal for
FCLK = 12 MHz)
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1024 ms
2048 ms
12 AT89S8253
3286H–MICRO–9/05
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