AT89S8253-24SC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89S8253-24SC Datasheet PDF : 59 Pages
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AT89S8253
8.1 Watchdog Control Register
The WDTCON register contains control bits for the Watchdog Timer (shown in Table 8-2).
Table 8-2. WDTCON – Watchdog Control Register
WDTCON Address = A7H
Not Bit Addressable
Reset Value = 0000 0000B
PS2
PS1
PS0
WDIDLE
DISRTO
HWDT
WSWRST
WDTEN
Bit
7
6
5
4
3
2
1
0
Symbol
PS2
PS1
PS0
WDIDLE
DISRTO
HWDT
WSWRST
WDTEN
Function
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K machine cycles, (i.e. 16 ms at a XTAL frequency of 12 MHz in normal mode or 6 MHz in x2 mode). When
all three bits are set to 1, the nominal period is 2048K machine cycles, (i.e. 2048 ms at 12 MHz clock frequency in
normal mode or 6 MHz in x2 mode).
Enable/disable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When
WDIDLE = 1, WDT freezes while the device is in IDLE mode.
Enable/disable the WDT-driven Reset Out (WDT drives the RST pin). When DISRTO = 0, the RST pin is driven high
after WDT times out and the entire board is reset. When DISRTO = 1, the RST pin remains only as an input and the
WDT resets only the microcontroller internally after WDT times out.
Hardware mode select for the WDT. When HWDT = 0, the WDT can be turned on/off by simply setting or clearing
WDTEN in the same register (this is the software mode for WDT). When HWDT = 1, the WDT has to be set by writing
the sequence 1EH/E1H to the WDTRST register (with address 0A6H) and after being set in this way, WDT cannot be
turned off except by reset, warm or cold (this is the hardware mode for WDT). To prevent the hardware WDT from
resetting the entire device, the same sequence 1EH/E1H must be written to the same WDTRST SFR before the
timeout interval.
Watchdog software reset bit. If HWDT = 0 (i.e. WDT is in software controlled mode), when set by software, this bit resets
WDT. After being set by software, WSWRST is reset by hardware during the next machine cycle. If HWDT = 1, this bit
has no effect, and if set by software, it will not be cleared by hardware.
Watchdog software enable bit. When HWDT = 0 (i.e. WDT is in software-controlled mode), this bit enables WDT when
set to 1 and disables WDT when cleared to 0 (it does not reset WDT in this case, but just freezes the existing counter
state). If HWDT = 1, this bit is READ-ONLY and reflects the status of the WDT (whether it is running or not).
Figure 8-1. Software Mode – Watchdog Timer Sequence
WDTEN
HW
HW
WSWRST
SW
SW
Writes
a1
13
3286H–MICRO–9/05
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