BT856 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

BT856

YCrCb or RGB to NTSC/PAL Digital Video Encoder

Unspecified 

Bt856/7

CIRCUIT DESCRIPTION

Video Timing

Reset

If the RESET* pin is held low during a single rising edge of the internally gener-

ated CLOCK signal, the subcarrier phase is set to zero, and the horizontal and ver-

tical counters are set to the beginning of VSYNC of FIELD1. Counting resumes

the first rising edge of CLOCK after rising RESET*.

In addition to the timing reset, if the RESET* pin is held low for two consecu-

tive low-to-high transitions of CLOCK, a software reset occurs, setting all of the

software programmable registers’ bits to zero.

Master Mode

Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from in-

ternal timing and from optional software bits. HSYNC* and VSYNC* are output

following the rising edge of CLOCK.

The horizontal counter is incremented on the rising edge of CLOCK. After

reaching the appropriate value (determined by the mode of operation), it is reset to

one, indicating the start of a new line.

The vertical counter is incremented at the start of each new line. After reaching

the appropriate value (determined by the mode of operation), it is reset to one, in-

dicating the start of a new field (interlaced operation) or frame (noninterlaced op-

eration).

The HSYNC* output may be configured to have standard video timing (4.7 µs

wide, asserted at start of a line default after RESET cycle) or it may be pro-

grammed to specify the start of HSYNC* (10-bit value) and the end of HSYNC*

(10-bit value). VSYNC* is asserted for 3 or 2.5 scan lines for 262/525 line and

312/625 line, respectively. When HSYNC* is configured for standard video tim-

ing, coincident falling edges of HSYNC* and VSYNC* indicate the beginning of

an odd field.

Slave Mode

Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are inputs that are regis-

tered on the rising edge of CLOCK.

The horizontal counter is incremented on the rising edge of CLOCK. A falling

edge of HSYNC* resets it to one, indicating the start of a new line.

The vertical counter is incremented on the falling edge of HSYNC*. A falling

edge of VSYNC* resets it to one, indicating the start of a new field (interlaced op-

eration) or frame (noninterlaced operation).

A falling edge of VSYNC* that occurs within ±1/4 of a scan line from the fall-

ing edge of HSYNC* indicates the beginning of an odd field. A falling edge of

VSYNC* that occurs within ±1/4 scan line from the center of the line indicates the

beginning of an even field. Referring to Figures 3–6, start of VSYNC occurs on the

falling HSYNC* at the beginning of the next expected odd field and halfway be-

tween expected falling HSYNC* edges at the beginning of the next expected even

field.

The operating mode is automatically determined when configured as a slave.

The PAL, INTERLACE, and SQUARE pins are ignored. The mode override reg-

isters can still be used to force a particular mode. 525-line operation is assumed;

625-line operation is detected by the number of lines in a field. Interlaced opera-

tion is detected by observing the sequence of odd or even fields; if the field timing

(odd follows odd, even follows even) is repeated, then noninterlaced mode is as-

Brooktree®

11

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