CDB5339 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5339 Datasheet PDF : 34 Pages
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CS5336, CS5338, CS5339
Certain serial modes align well with various inter-
face requirements. A CS5339 in MASTER mode,
with an inverted L/R signal, generates I2S
(Philips) compatible timing. A CS5336 in MAS-
TER mode, using FSYNC, interfaces well with a
Motorola DSP56000. A CS5336 in SLAVE mode
emulates a CS5326 style interface, and also links
up to a DSP56000 in network mode.
Analog Connections
The analog inputs are presented to the modulators
via the AINR and AINL pins. The analog input
signal range is determined by the internal voltage
reference value, which is typically -3.68 volts.
The input signal range therefore is typically
± 3.68 volts.
The ADC samples the analog inputs at
3.072 MHz for a 12.288 MHz ICLKD (CMODE
low). For the CS5336, the digital filter rejects all
noise between 26 kHz and (3.072 MHz-26 kHz).
For the CS5338 and CS5339, the digital filter re-
jects all noise between 28 kHz and
(3.072 MHz-28 kHz). However, the filter will not
reject frequencies right around 3.072 MHz (and
multiples of 3.072 MHz). Most audio signals do
not have significant energy at 3.072 MHz. Never-
theless, a 51 Ω resistor in series with the analog
input, and a 10 nF NPO or COG capacitor to
ground will attenuate any noise energy at 3.072
MHz, in addition to providing the optimum
source impedance for the modulators. The use of
capacitors which have a large voltage coefficient
(such as general purpose ceramics) should be
avoided since these can degrade signal linearity. If
active circuitry precedes the ADC, it is recom-
mended that the above RC filter is placed between
the active circuitry and the AINR and AINL pins.
The above example frequencies scale linearly with
output word rate.
The on-chip voltage reference output is brought
out to the VREF pin. A 10 µF electrolytic capaci-
tor in parallel with a 0.1 µF ceramic capacitor
attached to this pin eliminates the effects of high
frequency noise. Note the negative value of VREF
when using polarized capacitors. No load current
may be taken from the VREF output pin.
The analog input level used as zero during the
offset calibration period (described later) is input
on the ZEROL and ZEROR pins. Typically, these
pins are directly attached to AGND. For the ulti-
mate in offset nulling, networks can be attached to
ZEROR and ZEROL whose impedances match
the impedances present on AINL and AINR.
Power-Down and Offset Calibration
The ADC has a power-down mode wherein typi-
cal consumption drops to 150 µW. In addition,
exiting the power-down state initiates an offset
calibration procedure.
APD and DPD are the analog and digital power-
down pins. When high, they place the analog and
digital sections in the power-down mode. Bring-
ing these pins low takes the part out of
power-down mode. DPD going low initiates a
calibration cycle. If not using the power down
feature, APD should be tied to AGND. When us-
ing the power down feature, DPD and APD may
be tied together if the capacitor on VREF is not
Cal Period
(4096 x L/R clocks)
(85.33 ms @ 48kHz)
Filter Delay Time
(~40 L/R periods)
(~2 ms @ 48 kHz)
DPD
Normal Operation
DCAL
3-48
Figure 6. Initial Calibration Cycle Timing
DS23F1
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