CDB5339 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CDB5339

16-Bit, Stereo A/D Converters for Digital Audio

Cirrus Logic 

CS5336, CS5338, CS5339

SWITCHING CHARACTERISTICS

(TA = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF)

Parameter

Symbol Min

Typ

Max

Unit

ICLKD Period (CMODE low)

(Note 6)

ICLKD Low (CMODE low)

ICLKD High (CMODE low)

ICLKD rising to OCLKD rising (CMODE low)

ICLKD Period (CMODE high)

ICLKD Low (CMODE high)

ICLKD High (CMODE high)

ICLKD rising or falling to OCLKD rising (CMODE high, Note 4)

ICLKD rising to L/R edge (CMODE low, MASTER mode)

ICLKD rising to FSYNC edge (CMODE low, MASTER mode)

ICLKD rising to SCLK edge (CMODE low, MASTER mode)

ICLKD falling to L/R edge (CMODE high, MASTER mode)

ICLKD falling to FSYNC edge (CMODE high, MASTER mode)

ICLKD falling to SCLK edge (CMODE high, MASTER mode)

SCLK rising to SDATA valid (MASTER mode, Note 5)

SCLK duty cycle (MASTER mode)

t clkw1

78

t clkl1

31

t clkh1

31

t io1

5

t clkw2

52

t clkl2

20

t clkh2

20

t io2

5

t ilr1

5

t ifs1

5

t isclk1

5

t ilr2

5

t ifs2

5

t isclk2

5

t sdo

0

40

-

3906

ns

-

-

ns

-

-

ns

-

40

ns

-

2604

ns

-

-

ns

-

-

ns

-

45

ns

-

50

ns

-

50

ns

-

50

ns

-

50

ns

-

50

ns

-

50

ns

-

50

ns

50

60

%

SCLK rising to L/R (MASTER mode, Note 5)

t mslr

-20

SCLK rising to FSYNC (MASTER mode, Note 5)

t msfs

-20

SCLK Period (SLAVE mode)

t sclkw

155

SCLK Pulse Width Low (SLAVE mode)

t sclkl

60

SCLK Pulse Width High (SLAVE mode)

SCLK rising to SDATA valid (SLAVE mode, Note 5)

t sclkh

60

t dss

-

L/R edge to MSB valid (SLAVE mode)

t lrdss

-

Falling SCLK to L/R edge delay (SLAVE mode, Note 5)

t slr1

30

L/R edge to falling SCLK setup time (SLAVE mode, Note 5)

t slr2

30

Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5)

t sfs1

30

Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5)

t sfs2

30

DPD pulse width

t pdw 2 x tclkw

DPD rising to DCAL rising

t pcr

-

DPD falling to DCAL falling (OWR = Output Word Rate)

t pcf

-

Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2).

5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339.

6. Specifies minimum output word rate (OWR) of 1 kHz.

-

-

-

-

-

-

-

-

-

-

-

-

-

4096

20

ns

20

ns

-

ns

-

ns

-

ns

50

ns

50

ns

-

ns

-

ns

-

ns

-

ns

-

ns

50

ns

-

1/OWR

3-42

DS23F1

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