CDB5339 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5339 Datasheet PDF : 34 Pages
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CS5336, CS5338, CS5339
GENERAL DESCRIPTION
The CS5336, CS5338, and CS5339 are 16-bit, 2-
channel A/D converters designed specifically for
stereo digital audio applications. The devices use
two one-bit delta-sigma modulators which simul-
taneously sample the analog input signals at a 64
X sampling rate. The resulting serial bit streams
are digitally filtered, yielding pairs of 16-bit val-
ues. This technique yields nearly ideal conversion
performance independent of input frequency and
amplitude. The converters do not require difficult-
to-design or expensive anti-alias filters, and do not
require external sample-and-hold amplifiers or a
voltage reference.
An on-chip voltage reference provides for an in-
put signal range of ± 3.68 volts. Any zero offset is
internally calibrated out during a power-up self-
calibration cycle. Output data is available in serial
form, coded as 2’s complement 16-bit numbers.
Typical power consumption of only 400 mW can
be further reduced by use of the power-down
mode.
For more information on delta-sigma modulation
and the particular implementation inside these
ADCs, see the references at the end of this data
sheet.
L/R
(kHz)
32
32
44.1
44.1
48
48
CMODE
low
high
low
high
low
high
ICLKD
(MHz)
OCLKD/
ICLKA
(MHz)
8.192 4.096
12.288 4.096
11.2896 5.6448
16.9344 5.6448
12.288 6.144
18.432 6.144
SCLK
(MHz)
2.048
2.048
2.8224
2.8224
3.072
3.072
Table 1. Common Clock Frequencies
DS23F1
SYSTEM DESIGN
Very few external components are required to sup-
port the ADC. Normal power supply decoupling
components, voltage reference bypass capacitors
and a single resistor and capacitor on each input
for anti-aliasing are all that’s required, as shown
in Figure 1.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter, and is used to generate the
modulator sampling clock. ICLKD frequency is
determined by the desired Output Word Rate
(OWR) and the setting of the CMODE pin.
CMODE high will set the required ICLKD fre-
quency to 384 X OWR, while CMODE low will
set the required ICLKD frequency to 256 X
OWR. Table 1 shows some common clock fre-
quencies. The digital output clock (OCLKD) is
always equal to 128 X OWR, which is always
2 X the input sample rate. OCLKD should be
connected to ICLKA, which controls the input
sample rate.
The phase alignment between ICLKD and
OCLKD is determined as follows: when CMODE is
ICLKD
Input
01234567
DPD
Inp_ut
L/ R
Input
*
1 **
OCLKD 1
Ou_tput
L/ R
2
Input
***
OCLKD 2
Output
* DPD low is recognized on the next ICLKD rising edge (#0)
** L/R rising before ICLKD rising #2 causes OCLKD -1
*** L/R rising after ICLKD rising #2 causes OCLKD - 2
Figure 2. ICLKD to OCLKD Timing with CMODE
high (384 X OWR)
3-45
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