CXA1898Q View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXA1898Q

Recording/Playback Equalizer Amplifier

Sony Semiconductor 

CXA1898Q

Item

Measurement conditions

Min.

Low level input

voltage

VIL (LATCH/CLK/DATA/XRESET)

(Pins 23, 24, 25, 26)

0.0

High level input

voltage

VIH (LATCH/CLK/DATA/XRESET)

(Pins 23, 24, 25, 26)

3.5

Low level output

voltage

VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16,

17, 18, 19, 20, 21, 22)

0.0

High level output off-

leak current

IOZ Leak current which flows to the output

pin when Ioz output is open; applied

voltage is 10V.

—

Maximum clock frequency (1) fCK

500

Minimum clock pulse

width

(2) tWC

—

Minimum reset pulse

width

(3) tWR

—

Minimum data setup

time

(4) tSDK (DATA → CLK)

—

Minimum data hold

time

(5) tHCD (CLK → DATA)

—

Minimum data pulse

width

(6) tWD

—

Minimum latch setup

time

(7) tSLD (LATCH → DATA)

—

Minimum latch hold

time

(8) tHCL (CLK → LATCH)

—

Minimum clock hold

time

(9) tHLC (LATCH → CLK)

—

Note) • VDD is CPU supply voltage 5.0V.

• The maximum value for VDD is Pin 35 (VCC) voltage.

• For high level output off leak current, VCC is 10.0V.

Typ.

—

—

—

—

—

—

—

—

—

—

—

—

—

Max. Unit

1.5

VDD

V

0.5

1.0

µA

—

kHz

1.0

1.0

1.0

1.0

µs

2.0

1.0

1.0

1.0

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