CY7C1069AV33 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1069AV33 Datasheet PDF : 9 Pages
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CY7C1069AV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[3]
IIX
Input Leakage Current GND < VI < VCC
IOZ
Output Leakage Current GND < VOUT < VCC, Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
CE2 < VIL,
Power-down Current Max. VCC, CE1 > VIH
—TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE
CE2 < 0.3V, Max. VCC,
Power-down Current CE1> VCC – 0.3V,
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
–10
Min. Max.
2.4
0.4
2.0 VCC + 0.3
–0.3
0.8
–1
+1
–1
+1
275
70
50
–12
Min. Max. Unit
2.4
V
0.4
V
2.0 VCC + 0.3 V
–0.3
0.8
V
–1
+1
µA
–1
+1
µA
260
mA
70
mA
50
mA
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
TSOP II
FBGA
Unit
6
8
pF
8
10
pF
AC Test Loads and Waveforms[5]
OUTPUT
Z0= 50Ω
(a)
50Ω
VTH = 1.5V
30 pF* *Capacitive Load consists of all
components of the test environment
3.3V
All input pulses
90%
3.3V
R1 317 Ω
OUTPUT
5 pF*
*Including
jig and
scope
(b)
90%
R2
351Ω
GND
Rise time > 1V/ns
10%
(c)
10%
Fall time: > 1V/ns
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05255 Rev. *F
Page 3 of 9
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