7C1360A-150 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

7C1360A-150

256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

Cypress Semiconductor 

CY7C1360A

CY7C1362A

Selection

Circuitry

TDI

0

Bypass Register

210

Instruction Register

Selection

Circuitry

TDO

31 30 29 . . 2 1 0

Identification Register

x.

. . . 210

Boundary Scan Register [12]

TDI

TAP Controller

TDI

Figure 2. TAP Controller Block Diagram

TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)

Parameter

Description

Test Conditions

Min.

Max.

Unit

VIH

Input High (Logic 1) Voltage[13, 14]

VIl

Input Low (Logic 0) Voltage[13, 14]

2.0

VCC + 0.3

V

–0.3

0.8

V

ILI

Input Leakage Current

0V < VIN < VCC

–5.0

5.0

µA

ILI

TMS and TDI Input Leakage Current 0V < VIN < VCC

–30

30

µA

ILO

VOLC

VOHC

VOLT

VOHT

Output Leakage Current

LVCMOS Output Low Voltage[13, 15]

LVCMOS Output High Voltage[13, 15]

LVTTL Output Low Voltage[13]

LVTTL Output High Voltage[13]

Output disabled,

0V < VIN < VCCQ

IOLC = 100 µA

IOHC = 100 µA

IOLT = 8.0 mA

IOHT = 8.0 mA

–5.0

VCC – 0.2

2.4

5.0

µA

0.2

V

V

0.4

V

V

Notes:

12. X = 69 for the x36 configuration;

X = 50 for the x18 configuration.

13. All voltage referenced to VSS (GND).

14. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) < – 0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for

t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than

tKHKL (min.).

15. This parameter is sampled.

Document #: 38-05258 Rev. *A

Page 14 of 28

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